The present invention relates to a method of manufacturing a semiconductor device such as a power IC which includes lateral unit structures with high breakdown voltage. More specifically, the present invention relates to a method of manufacturing a semiconductor device which exhibits a breakdown voltage of 20 V or more.
In many conventional power IC's, a plurality of high-breakdown-voltage devices are integrated on one single chip. In the high-breakdown-voltage device, a drain side portion of a gate electrode is extended onto a LOCOS (local oxidation of silicon) film for device separation to relax the electric field localization below the drain-side edge of the gate electrode.
Recently, the structure of each high-breakdown-voltage device integrated on a chip has become so fine that the size of the constituent device affects greatly the down-sizing of the chip. When the LOCOS film for electric field relaxation is formed through an exclusive mask, an alignment mismatch of around 0.3 .mu.m is caused between the LOCOS film and the gate electrode, and the LOCOS film is elongated by the alignment mismatch. When the device pitch (distance between the source and the drain) is 4 .mu.m, for example, the chip size increases to 4.3 .mu.m, i.e. around 8% (0.3 .mu.m+4 .mu.m).
FIG. 11 is a cross section of a main portion of a conventional lateral type DMOSFET with a high breakdown voltage. Here, the DMOSFET strands for "dual diffusion metal oxide semiconductor field effect transistor".
Referring now to FIG. 11, a p-type base region 23 and an n-type offset region 21 are formed in the surface portion of a p-type silicon substrate 1. An n-type source region 24 is formed in the surface portion of the p-type base region 23. A polysilicon gate electrode 27a is formed above the p-type base region 23 and the p-type silicon substrate 1 between the n-type source region 24 and the n-type offset region 21 with a gate oxide film 2 interposed inbetween. The gate electrode 27a is extended onto a part of a LOCOS film 6a formed on the n-type offset region 21. An n-type drain region 22 and a drain electrode 25 are formed on the right hand side of the n-type offset region 21. Since LOCOS film 6a and gate electrode 27a are patterned through individual or different masks, the foregoing patterning mismatch (alignment mismatch) occurs. Due to the alignment mismatch, the overlap length D of the gate electrode 27a and LOCOS film 6a is elongated. As the overlap length D becomes longer, it is necessary to elongate the LOCOS film 6a for obtaining the design value of the breakdown voltage. As the device structure becomes finer as described above, the alignment mismatch can not be ignored. The device pitch (distance between the source and the drain) W becomes longer by the increment of the length of the LOCOS film 6. The elongated device pitch enlarges the chip size.
As described above, the conventional technique causes the alignment mismatch as the device structure becomes finer. The alignment mismatch further causes the chip size increase.
In view of the foregoing, it is an object of the invention to provide a method of manufacturing a lateral type semiconductor device which facilitates shortening the device pitch without enlarging the chip size.